1. Field of the Invention
The present invention relates to a complementary semiconductor device and, more particularly, to a complementary semiconductor device in which a field effect transistor isolates a P type semiconductor device region and an N type semiconductor device region.
2. Description of the Background Art
Device isolation between semiconductor devices is performed using a LOCOS (Local Oxidation of Silicon) method, as seen in, for example, Japanese Patent Laying-Open Gazette No. 190869/1987. Isolation between a P type semiconductor device region and an N type semiconductor device region in a complementary semiconductor integrated circuit device has been also performed using the LOCOS method.
FIGS. 3A to 3C are views showing a method for forming on a step by step basis a device isolating film using the LOCOS method. Referring to FIG. 3A, an oxide silicon film 112 is formed on a main surface of a P type silicon substrate 1. Then, a silicon nitride film 111 is formed within the range in which an active region is formed (the range is shown by l.sub.o in FIG. 3A). When the substrate 1 is subjected to thermal oxidation in this state, a thick device isolating film 12 is formed at a region in which the silicon nitride film 111 was not formed as shown in FIG. 3B, because oxidation-proof property of the silicon nitride film is strong. Then, the silicon nitride film 111 and the silicon oxide film 112 are removed from the main surface of the substrate 1. As a result, as shown in FIG. 3C, an active region (shown by 1 in FIG. 3C) is formed.
However, when a device isolating film 12 is formed by a LOCOS method, an encroachment on the active region called bird's beak (the portion shown by C in the figure) is formed at the end portions of the device isolating film. Therefore, actually obtained length l of the active region is considerably smaller than the originally intended length l.sub.o of the active region. As a result, when the device isolation is performed by a LOCOS method, it is difficult to miniaturize the devices. In addition, if the thickness of the device isolating film is thin to control the bird's beak, there the ability to isolate devices is deteriorated.
In order to cope with the miniaturization of the devices, a method for isolating devices using a field shield isolation is seen in, for example Japanese Patent Laying-Open Gazetted No. 47437/1985. An example in which a well and a substrate are isolated by the field shield method is seen in Japanese Patent Laying-Open Gazette NO. 79740/1985. FIG. 3D is a schematic sectional view of a semiconductor device in which a well and a substrate are isolated using the field shield electrode which is seen in the same gazette. Referring to FIG. 3D, a semiconductor device comprising a device isolating region, in which a LOCOS method suitable for the conventional miniaturization is used, comprises an N type silicon substrate 11, a P type well layer 17, a device isolating film 12 formed at the junction with the P type well layer 17 on the N type silicon substrate 11 and a shield electrode 19 formed on the device isolating film 12. A wiring electrode 16 is formed on the shield electrode 19 through an interlayer insulating film 15. An N channel MOSFET 14 is formed on the P type well layer 17 and a P channel MOSFET 13 is formed on the N type silicon substrate 11. The N channel MOSFET 14 comprises an N type source/drain region 22 and a gate electrode 21 formed between the N type source/drain regions 22 through a gate oxide film 20. The P channel MOSFET 13 comprises a P type source/drain region 18 and a gate electrode 21 formed between the P type source/drain regions 18 through a gate oxide film 20. When the device is miniaturized, it is likely that a depletion layer between the P type well layer 17 and the P type source/drain region 18 of the P channel MOSFET 13 formed on the main surface of the N type silicon substrate could be connected. In order to avoid this connection, the shield electrode 19 is formed on the device isolating film 12 and the shield electrode 19 is fixed to, for example, the potential Vcc.
According to this device isolating method, since the shield electrode 19 is formed on a thick field oxide film which was formed by the conventional LOCOS method, it is necessary to align the resist with the field oxide film by photolithography. Since a step portion generated by the field oxide film is big, an upper wiring could be broken. Since the thickness of the device isolating film 12 is thick, a field effect by the shield electrode 19 is not achieved enough. As a result, this device isolating method is not suitable for the miniaturization of a device.
In order to solve the above described problems, a method for forming a field shield electrode for isolating wells and its oxide film on the same layer as that of a gate electrode is disclosed in Japanese Patent Laying-Open Gazette No. 169163/1985. FIG. 4 is a sectional view of the semiconductor device shown in the gazette. Referring to FIG. 4, a P channel MOSFET 13 formed on the main surface of an N type silicon substrate 11 and an N channel MOSFET 14 formed on the main surface of a P type well layer 17 are isolated by one field effect transistor 220. The P channel MOSFET 13 comprises a P type source/drain region 18, and a polysilicon gate 204 formed between the P type source/drain regions 18 through a gate oxide film 206. The N channel MOSFET 14 comprises an N type source/drain region 22 and a polysilicon gate 205 between the N type source/drain regions 22 through a gate oxide film 206. The field effect transistor 220 for isolation comprises either one region 18 of the P type source/drain regions formed on the main surface of the N type silicon substrate 11, either one region 22 of the N type source/drain regions formed on the main surface of the P type well layer 17 and a polysilicon layer 207 formed at the junction between the N type silicon substrate 11 and the P type well layer 17 on the main surface of the N type silicon substrate 11 through he gate oxide film 219. A polysilicon gate 204 serving as a gate electrode of the P channel MOSFET 13, a polysilicon gate 205 serving as a gate electrode of the N channel MOSFET and a polysilicon layer 207 serving as a gate electrode of the field effect transistor 220 for isolating devices are formed on the same polysilicon layer. Either one region 22 of the N type source/drain region of the N channel MOSFET 14 and either one region 18 of the P type source/drain regions of the P channel MOSFET 13 are connected by a metal wiring 214. However, the well isolation in this structure is not perfect. The reason is described hereinafter.
FIG. 5A is a schematic view in case where the well isolation in a twin well structure on a P type substrate often used in a DRAM is performed using a field shield electrode. Normally, an N type well layer 302 is fixed to the supply voltage V.sub.CC (positive potential). A P type well layer 303 and a P type substrate 301 are fixed to a substrate potential V.sub.BB (negative potential). If the field shield electrode 306 is fixed at the supply voltage V.sub.CC, a storage layer is formed on a substrate surface portion A on the N type well layer 302 beneath the field shield electrode type well layer 306 and an inversion layer is formed on the substrate surface portion B on the P type well layer 303. In this case, there is no problem at the substrate surface portion A, but the following problem arises when an N type diffusion layer 304 is brought to the ground potential V.sub.SS at the substrate surface portion B. That is, when the transistor having the N type well layer 302 as its drain, the N type diffusion layer 304 as its source and the field shield electrode 306 as its gate turns on, then a leak path is formed between the N type diffusion layer 304 and the N type well layer 302. The similar leak path is formed at the substrate surface portion A on the same principle when the field shield electrode 306 is brought to the substrate potential V.sub.BB.
FIG. 5B is a graph schematically showing the relation between a potential V.sub.F of the field shield electrode 306 and a leak current I.sub.D. An abscissa shows a potential of the field shield electrode 306 and ordinate shows a leak current value when the substrate surface A or the substrate surface B serves as a channel. When the field shield electrode 306 is fixed to the ground potential V.sub.SS, the leak current does not flow on the substrate surface A or the substrate surface B. However, the potential of the field shield electrode actually fluctuates due to capacity coupling between diffusion portions formed on opposite sides, an upper wiring and the like. When the fluctuated potential exceeds a threshold voltage V.sub.thp or V.sub.thN of the field effect transistor formed on the substrate surface A or the substrate surface B, the leak current flows again. In order to prevent the leak current from generating, both absolute values of the threshold voltage V.sub.thP on the side of the P channel and the threshold voltage V.sub.thN on the side of the N channel have to be set high. As a result, it becomes difficult to set a process parameter for determining a threshold voltage and also it becomes difficult to determine the length of the field shield electrode 306 at the time of setting and the width of the device isolating region comprising the field shield electrode and the diffusion layer. The above mentioned problem always arises when the well isolation is performed by one shield electrode. According to this method, since the gate electrode for the field shield for isolation and the gate electrodes of the P channel MOSFET and the N channel MOSFET are formed on the same layer, a design thereof is considerably limited.
FIG. 6 is a schematic sectional view showing the well isolation using both field shield isolation and trench isolation seen in Japanese Patent Laying-Open Gazette No. 290753/1986. Referring to FIG. 6, an N channel MOSFET 14 formed on a main surface of a P type silicon substrate 401 and a P channel MOSFET 13 formed on a main surface of an N type well layer 402 are isolated by field shield electrodes 404 and 405 and a trench 409. The field shield electrode 405 is held at a first potential V.sub.1 and the field shield electrode 404 is held at a second potential V.sub.2. Since the well isolating method shown in FIG. 6 uses both the field shield isolation and the trench isolation, the capability of isolating devices is high, but it is necessary to form a trench, with the result that a manufacturing process becomes complicated. In addition, there is a problem that the area of the region in which the trench is formed is reduced from the area of the active region.